1. Field of the Invention
The present invention relates to a multiplex conversion apparatus in a digital synchronous network, more particularly relates to a time slot assignment (TSA) circuit for setting channels in such a multiplex conversion apparatus.
In a digital synchronous network, it is possible to set channels in the time domain (interchange the positions of channels in the rows of time slots) by assignment of time slots at a digital multiplex level (for example, synchronous transport signal (STS)-12, STS-48, etc.) and as a result it is possible to realize a multiplex conversion apparatus. The present invention deals with such a TSA circuit, in particular a TSA circuit which can easily handle increases in the transmission rate and increases in the volume of transmission and operates with high efficiency and offers a high degree of freedom in combination of channel settings.
2. Description of the Related Art
With the rate of transmission and the volume of communication both expected to increase in the future, a transmission system which is high in efficiency and which offers a high degree of freedom in combination of channel settings is being demanded. Along with the increase in the volume of communications, however, both the size of the circuit of course and also the number of channels have been increasing and as a result the number of combinations of channel settings has increased as well. If attempting to realize such combinations with the circuit of the related art, explained later, however, the number of nets becomes tremendous and the margin in timing becomes insufficient. Further, the layout on the chip becomes difficult. These and other difficulties can obstruct development.
While there have been remarkable advances made in the technology for integration of large size integrated circuits (LSIs) in recent years, there are still various limitations. These limitations are obstacles in realizing a TSA function in circuit design. More specifically, in the case of STS-48 (2.4 Gbps) level TSA (setting of channels), that is, STS-48 TSA, of the related art, it was sufficient to realize 2304 combinations of channels. As opposed to this, in the future with STS-192 TSA, it will be necessary to realize 36,864 combinations of channels. Consequently, the circuit would have to be 16 times the size of that for STS-48 TSA.
In addition to this increase in the size of the circuit, the rate of transmission (bit rate of signals to be processed) is also becoming higher, so naturally the power consumption is also increasing.
Consequently, if the conventional configuration of a TSA circuit comprised of only logic circuits is applied as it is to STS-192 TSA, there would be the problem of disadvantages in terms of the circuit size, power consumption, margin of timing, and degree of integration on the chip (number of nets) etc.
In view of this situation, as will be explained in detail later, the present invention first of all splits off and makes independent the TSA circuit. This split off independent TSA circuit is comprised of a working side TSA circuit and a protection side TSA circuit.
A look at these working side TSA circuit and protection side TSA circuit shows that in the conventional TSA circuit (2.4 Gbps), processing was performed in units of bytes and when the volume of transmission increases about 16 (=40/2.4)-fold, the above-mentioned number of combinations of channels would become a large 589,824. If using the conventional configuration of a TSA circuit as it is, simulation shows that the size of the circuit would increase 256-fold and that there would be the problem of an extreme difficulty in realizing the TSA circuit (40 Gbps) from the viewpoint of the margin layout etc.
The above TSA circuit (40 Gbps) is an independent working/protection type TSA circuit constituted by a mutually independent working side TSA circuit part and protection side TSA circuit part. That is, it is a TSA circuit in which TSA is neither performed from the working side to the protection side nor performed from the protection side to the working side.
Some users, however, may demand that TSA be also performed between the working side transmission data (40 Gbps) and the protection side transmission data (40 Gbps).
Such a mixed working/protection type TSA circuit would be an 80 (=40+40) Gbps TSA circuit. As explained above, the TSA circuit (2.4 Gbps) of the related art performs processing in byte units, so if the transmission volume increases as large as about 32 (=80/2.4)-fold, the number of combinations of channels would reach 2,359,296. Therefore if the conventional configuration of a TSA circuit is applied as it is, simulation shows that the circuit would increase in size 1024-fold and there would be the problem of realization of such a TSA circuit (80 Gbps) becoming substantially impossible from the viewpoint of the margin layout etc.
Accordingly, in consideration of the above problems, an object of the present invention is to provide a high speed and large capacity TSA circuit able to be realized by combination of a plurality of identical modular circuits without causing a tremendous increase in the size of the circuit.
To attain the above object, the present invention provides a TSA circuit which receives as input upper side incoming transmission data from a super high speed ring network and lower side incoming transmission data from a high speed ring network and outputs upper side outgoing transmission data to the super high speed ring network and lower side outgoing transmission data to the high speed ring network. The TSA circuit is provided with a TSA function block which has a time switch and a space switch to produce outgoing transmission data obtained by interchanging channels for the incoming transmission data in units of bits.
Due to this, a TSA circuit is realized which performs TSA processing on high speed and large volume incoming transmission data to interchange channels and output the resultant outgoing transmission data by a relatively small sized circuit configuration.